THE PRELIMINARY ORAL EXAMINATION FOR THE DEGREE OF Ph.D. IN
COMPUTER SCIENCE FOR
James M. Stevens
In the last decade, flash memory has matured from thumb drives and digital camera memory chips into new applications such as smart phones, solid state drives (SSDs) capable of replacing hard disks, and caches in high performance server storage arrays. These new applications are enabled by the density and low cost per bit of modern NAND flash memory devices. In the storage hierarchy, flash is particularly useful for reducing the average latency of accesses because its read access time is 2-3 orders of magnitude faster than hard disks. Flash also offers more physical durability, smaller form factor, and lower power compared to hard disks. Combined, these advantages are currently revolutionizing the computing landscape by significantly improving storage system performance in traditional PC and server systems and enabling entirely new types of mobile computing devices such as smart phones and tablets.
As flash has revolutionized the storage system, researchers have also proposed using it and other proposed non-volatile memory (NVM) technologies directly in the memory hierarchy. The insight is that the NVM technologies are fast enough that the hardware interfaces and software abstractions used to access the storage system create unnecessary overhead. Instead, the research community has proposed creating a hybrid main memory system using both traditional DRAM and NVM. This proposal assumes a hybrid main memory system consisting of a DRAM caching NAND flash and both types of memory are managed directly by the memory controller.
Operating systems have evolved for the last several decades with specific assumptions about the memory and storage hierarchies. Since hybrid memories merge the memory and storage hierarchies and have much faster latencies than traditional hard disks, the assumptions operating systems make must be revisited to ensure that the best possible performance is achieved. The early work in hybrid memories has focused on the memory controller and has left the implications on the OS largely unexplored.
This thesis intends to examine several areas in which the interactions between the OS and the memory controller can be improved to optimize system performance in hybrid memory architectures. In particular, this thesis will focus on identifying bottlenecks and information available at the system software level that can be used to improve the utilization of non-volatile memory. The first major task is to use our simulation environment, which is capable of simulating both advanced SSDs and future hybrid memory architectures, to quantify the overheads caused by the operating system when using SSDs and hybrid memories. The second task is to modify the virtual memory system to enable hints such as the TRIM commmand to be sent to the flash backing store of the hybrid memory, which allows the flash controller to be more effective. Third, we intend to leverage the data structures in the operating system scheduler to prefetch data from the flash backing store into DRAM before it is needed. Finally, we will implement support for memory system checkpointing in the OS and hybrid memory controller to determine if it is feasible to use hybrid DRAM/flash memories to help reduce checkpoint overhead and improve fault tolerance in supercomputers. We hope to show that these techniques result in a significant improvement in memory system capabilities and performance, as well as lay the groundwork for future exploration into operating system and hybrid memory system co-design.
Examining Committee:
Dr. Bruce Jacob - Chair
Dr. Clyde Kruskal - Dept’s Representative
Dr. Alan Sussman - Committee Member
Dr. Peter Keleher - Committee Member
EVERYBODY IS INVITED TO ATTEND THE PRESENTATION