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PLunch: Verified Lifting of Stencil Computations
Sankha Narayan Guria
Tuesday, October 29, 2019, 11:00 am-12:00 pm Calendar
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Weekly PL reading group discussing the paper "Verified Lifting of Stencil Computations". Discussion will be led by Sankha Narayan Guria. Paper available at https://homes.cs.washington.edu/~akcheung/papers/pldi16.pdf

This paper demonstrates a novel combination of program synthesis and verification to lift stencil computations from low-level Fortran code to a high-level summary expressed using a predicate language. The technique is sound and mostly automated, and leverages counter-example guided inductive synthesis (CEGIS) to find provably correct translations. Lifting existing code to a high-performance description language has a number of benefits, including maintainability and performance portability. Our experiments show that the lifted summaries allow domain specific compilers to do a better job of parallelization as compared to an off-the-shelf compiler working on the original code, and can even support fully automatic migration to hardware accelerators such as GPUs. We have implemented verified lifting in a system called STNG and have evaluated it using microbenchmarks, mini-apps, and real-world applications. We demonstrate the benefits of verified lifting by first automatically summarizing Fortran source code into a high-level predicate language, and subsequently translating the lifted summaries into Halide, with the translated code achieving median performance speedups of 4.1x and up to 24x as compared to the original implementation.

This talk is organized by Sankha Narayan Guria