Modular quantum computing architectures, composed of multiple chips or processors, have emerged as a practical route to scale up qubit counts beyond the engineering limitations of a single device. In such architectures, quantum processing units (QPUs) are networked via interconnects to act as one larger computer. This approach is being pursued by many leading platforms across most major qubit modalities.

Operations performed over quantum interconnects are necessarily slow and noisy compared to standard intra-processor gates. Although interconnect hardware is not yet mature, it is rapidly progressing toward integration with state-of-the-art systems. At the same time, the field is largely driven by experimental efforts, with comparatively limited attention to system-level design. Together, these factors create an opportunity for computer systems research to improve overall performance without requiring fundamental hardware advances.

In this proposal, I argue that a detailed understanding of quantum interconnect hardware can enable system-level optimizations to improve the end-to-end performance of near-term modular quantum computers. The proposed ideas center around careful modeling of interconnect hardware and optimal control of noisy link dynamics.